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Micrel, Inc.
KSZ9692PB, KSZ9692PB-S
List of Figures
Figure 3. KSZ9692PB, KSZ9692PB-S Functional Block Diagram ....................................................................................... 27
Figure 4. Static Memory Interface Examples ........................................................................................................................ 29
Figure 5. External I/O Interface Examples ............................................................................................................................ 29
Figure 6. 8-bit NAND Interface Examples............................................................................................................................. 30
Figure 7. 16-bit NAND Interface Examples........................................................................................................................... 31
Figure 8. Two 16-bit DDR Memory Device Interface Example ............................................................................................. 32
Figure 9. Two 8-bit DDR Memory Devices Interface Example ............................................................................................. 33
Figure 10. Burst DDR Read Timing ...................................................................................................................................... 34
Figure 11. Burst DDR Write Timing....................................................................................................................................... 34
Figure 12. USB 2.0 Configuration as Two-Port Host ............................................................................................................ 36
Figure 13. USB 2.0 Configuration as Host + Device............................................................................................................. 36
Figure 14. Reset Circuit ........................................................................................................................................................ 41
Figure 15. Power and Clocks ................................................................................................................................................ 41
Figure 16. Reset Timing........................................................................................................................................................ 43
Figure 17. Static Memory Read Cycle .................................................................................................................................. 43
Figure 18. Static Memory Write Cycle .................................................................................................................................. 44
Figure 19. External I/O Read and Write Cycles .................................................................................................................... 44
Figure 20. Ball Grid Array Map.............................................................................................................................................. 46
Figure 21. KSZ9692PB 400-Pin PBGA (24X24X2.33 MM) .................................................................................................. 47
Figure 22. KSZ9692PB-S 400-Pin PBGA (17X17X1.4 MM)................................................................................................. 48
May 2011
7
M9999-051111-4.0
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